The School of Electronics Engineering, KIIT-DU, in collaboration with the IEEE Test Technology Technical Community (TTTC) India, successfully organized a 3-Day Workshop on VLSI Testing from 31st October to 2nd November 2025. The workshop aimed to enhance knowledge and skills in VLSI Design-for-Testability (DFT) and Testing Methodologies, bringing together students, researchers, faculty, and industry professionals.
Renowned industry experts—Mr. Gaurav Bhargava from Qualcomm; Mr. Sameer Chillarlige from Cadence; Mr. Venkata Rangam Totakura from Infineon Technologies; and Dr. Rajit Karmakar from AMD conducted insightful technical sessions on fault modeling, scan-based testing, test generation, and memory testing. Participants also gained hands-on experience through lab sessions on industry-standard VLSI testing tools.
The event was inaugurated in the presence of Prof. (Dr.) Saranjit Singh, Vice Chancellor, KIIT-DU; and Prof. (Dr.) Jnyana Ranjan Mohanty, Registrar. Over 100 participants, including students, research scholars, faculty members, and industry professionals, attended the workshop. The sessions provided valuable exposure to modern semiconductor testing technologies, career opportunities, and research prospects in the VLSI domain.
Prof. (Dr.) Suprava Patnaik, Dean, SoEE, along with coordinators Prof. Arindam Basak, Dr. Manas Ranjan Tripathy, and other faculty members, led the successful organization of the workshop. The workshop concluded with a valedictory session and certificate distribution, marking a successful collaboration between KIIT-DU and TTTC India in fostering academic–industry engagement in semiconductor education.